This invention relates to digital video signal processing, and more particularly to the generation of a frequency agile clock signal for use with serial video signals in any one of a number of different standard video formats.
It is very convenient to be able to handle video formatted according any one of several video standards using only one serializing or deserializing integrated circuit. However, the serial data formats of the most widely used video standards operate at different data rates. D1 component digital video (CCIR 601/SMTE RP125) standard prescribes a clock frequency of 270.000 MHz, while D2 NTSC composite digital video operates at a clock frequency of 143.182 MHz and D2 PAL composite digital video operates at a clock frequency of 177.345 MHz. And, a proposed new standard prescribes a clock frequency of 360.000 MHz.
Prior approaches to producing a frequency agile clock generator to handle digital video in the three present standards have used a voltage controlled oscillator (VCO) that operates over the full range of the present standards, from 143 to 270 MHz. The need to operate over such a wide range of frequencies has made it necessary to use an RC type oscillator. However, RC type oscillators are difficult to implement in the VHF range and have a high degree of jitter as a result of their low Q of 1.
To reduce jitter, it would be preferable to use an LC type oscillator with a higher Q, 10 to 20 or more. LC type oscillators, however, do not generally have the wide range of frequency tunability required by this application. Three or four separate oscillators could be used, switching between them as necessary. Or, one oscillator circuit could be switched between three or four different LC resonators. However, both of these approaches are expensive in terms of component cost, circuit area and alignment. It would be very difficult to implement the switching function without degrading the oscillator's performance in some respect.